FPGA RTL Engineer and Programmer.
I'm a freelance Electrical Engineer who specialises in FPGA RTL design in SystemVerilog. I have been programming FPGAs in a full-time capacity since 2009. I also have a wide variety of experience in other RTL and conventional programming languages.
Designing a top-level full-system FPGA architecture. Designing a modular architecture for various FPGA subsystems and how they interconnect.
Preparation of an algorithm for optimal implementation on the FPGA; Converted from journal articles or existing code.
Implementation of RTL firmware in SystemVerilog or VHDL, for clock rates up to 644Mhz.
Host-side applications, utilities and testbenches which interface to the FPGA and perform configuration and testing functions.
Image and signal processing in Python using numpy, matplotlib and scipy.
Development of tcl scripts for project build automation, stored in github. Use of continuous integration tools to automatically build FPGA firmware binaries.
Optimising existing RTL projects to resolve timing issues, increase clock rates or reduce resource usage.
Producing training materials and one-on-one mentorship sessions for junior RTL engineers.
